Mr. Pradeep Kumaar aka Prady is the CEO and Co-Founder of NP Digital India, as well as the Founder and CEO of Stan Ventures. With over 15 years of experience in digital marketing, he has successfully built multiple companies from the ground up through bootstrapping. As a multi-agency owner in India, he focuses on expanding US-based growth strategies to maximize success for partners and clients. His expertise in organic search, sales, and psychology has been instrumental in driving the growth of his companies, which now employ over 650 marketers.

A visionary leader specializing in performance marketing, he has played a pivotal role in establishing NP Digital India as a leading industry player. Under his leadership, NP Digital India has won over 30 industry awards in the past two years, a testament to his strategic vision and execution. His goal is to position NP Digital India among the top five performance marketing agencies in India within three years while making a significant global impact. Beyond business, his motivational leadership extends to mentoring young entrepreneurs and exploring diverse cultures.

His journey is a story of determination and resilience. Coming from a low-middle-class background, he has built multiple million-dollar agencies without external support or investment. His success serves as an inspiration for aspiring professionals in the digital marketing industry. With his unwavering commitment to excellence and growth, he continues to be a driving force in the digital marketing landscape.

Introducing Mr. Hatim Kapadia. He is an accomplished and self-motivated leader with more than 21 years of experience managing, designing, and implementing application solutions, focusing on technology modernization and transformation. He believes we are what we repeatedly do. Excellence, then, is not an act but a habit.

He is a distinguished technology expert and leader with an exceptional track record in transforming large-scale legacy platforms into state-of-the-art, real-time processing systems. With a robust background in optimizing technology investments, driving innovation, and enhancing operational efficiency, he has made significant contributions to technology modernization. His remarkable career includes the development of a Regression Testing Framework for legacy payment applications, resulting in substantial cost savings and demonstrating his commitment to delivering impactful solutions. 

He has global experience, having worked for many leading top 500 Fortune companies in his career spanning across geography in India, Australia, and the USA, and has proven his ability to lead diverse teams and manage complex projects effectively. In addition to his technical expertise, he holds a Harvard certificate in Leadership Excellence. His leadership skills are further evidenced by his role in implementing continuous integration, real-time payment systems, and advanced DevOps practices.  He also has an original publication on applying technology in clinical diagnosis along with Deep Q-Networks based efficient two-way security system for intrusion detection in a cloud computing environment.

Mr. Amit Bagaria has authored 17 books, 8 of which have been No.1 bestsellers on Amazon. Being impressed with the quality of the extensive research in one of his books, Prime Minister Narendra Modi invited him to New Delhi for a 27-minute meeting. Apart from authoring 17 books, he has contributed chapters in 4 other books, and over 90 articles in 14 newspapers and magazines, including 7 cover stories in retail sector magazines.

An out-of-the-box thinker and marketing whiz, he has created a mark in different sectors, including MedTech; hospital planning and design; shopping mall planning, design and leasing; retail consulting; affordable housing; real estate marketing; and social media market research.

From 1998 to 2002, his company was India’s No.1 hospital and healthcare facility development consultant. From 2004 to 2015, his company Asipac was South India’s leading mall development consultant. Asipac also did residential project strategy, marketing, and exclusive selling in South India and Jaipur. It launched 19,000 affordable apartments in the most difficult (post-Lehman) period from 2008-2011. Asipac also handled luxury housing (₹5-15 crores) projects from 2009 to 2017 that broke all previous records in each city.

He has been featured in over 290 media articles in India, the USA, the UK, France, Brazil, and Hong Kong, including 25+ newspaper front pages and 45+ TV features or interviews. He has been a guest faculty/speaker at IIM Bangalore; Symbiosis University, Pune; KIAMS, Karnataka; and Tata Institute of Social Sciences, Mumbai. He has been a part of national committees of CII and FICCI, a Panel Moderator at over 20 industry events in India and abroad, a guest speaker at several more, and a jury member for several industry awards in different sectors. He has received 19 awards, including 7 international awards.

Mr. Vijayaprabhuvel Rajavel is a trailblazer in the field of ASIC Product Engineering and Design for Testability (DFT) of Semiconductor Integrated Circuits. With a Master’s degree in Electrical and Computer Engineering from Portland State University and a Bachelor’s in Electronics and Communication Engineering from Anna University, graduating in the First Class, his expertise spans scan compression, ATPG, memory testing, and VLSI DFT methodology development.

His career is marked by significant contributions to leading EDA companies like Cadence Design Systems, where he served as a Lead Product Engineer. He played a pivotal role in optimizing DFT flows for key customers, resolving critical technical challenges, and ensuring timely product releases. His expertise extended across the USA, EMEA, and APAC regions, leading to substantial improvements in scan chains for a Graphics project (4% to 96%). Additionally, he resolved complex issues in advanced scan stitching – physical and power-aware, IEEE 1500 wrapper implementation, and power domain violations debugging. His strategic product evaluations facilitated new customer acquisitions, driving recurring revenue and these efforts were acknowledged through “Creator”, “Explorer”, and “Elevate the Team” recognitions.

At Samsung Austin R&D Center, he earned the “Award of Excellence” for developing an ATPG flow that enabled early detection of design issues, saving significant time in the chip integration lifecycle. His innovative approach to DFT methodologies has consistently improved chip yield, reduced test time and cost, and enhanced overall product quality.

Beyond his professional achievements, he is passionate about education and mentorship. He has taught graduate students at Portland State University, mentored aspiring engineers, and also founded exploredft.com, a resource for DFT Engineers. As a Senior Member of IEEE, he actively contributes through conference engagements, journal peer reviewing, and serving as Session Chair and Technical Program Committee, reflecting his commitment to advancing semiconductor engineering.